Re: TED badlines, how do they work?

From: Segher Boessenkool <>
Date: Sun, 4 Sep 2011 18:31:21 +0200
Message-Id: <>
>>>>> After all, the 656x-VIC-II still needed +12V for parts of the chip
>>>>> (video output drivers?) where TED managed the same with a  
>>>>> single +5V
>>>>> supply (and produced more colors).
>>>> The power supply for the (analog) output stages, yeah. 8565 uses  
>>>> 5V as
>>>> well, I'm not sure why the 6569 needed 12V.
>>> No idea either... But I have a C64 with a 6569R3 (in ceramic :))  
>>> where
>>> the +12V supply was broken. Due to a dead capacitor the VIC only got
>>> +8V. I still got a picture, but the colors were pale and went
>>> completly away when the chip warmed up, giving a pure B/W picture.
>>> Otherwise the system was working fine. Replacing the dead capacitor
>>> restored +12V and fixed the color issue.
>> Would be interesting to know whether amplifying the output would have
>> helped as well :-)
> LUMA was OK and didn't change after fixing the +12V supply. Just  
> for fun I measured power consumption on +12V for the 6569R5 (4786  
> 15) on my testboard. It draws 34-35 mA on +12V alone.

It turns out the (internal) clock drivers and a few other things use  
the 12V
supply on the 6569 (those use the normal supply on the 8565).  Those  
can sink
a lot of current I bet ;-)

>> They added some test pads and did some minor cleanups to the
>> routing/layout.
>> Perhaps the analog stuff is dimensioned differently as well, I  
>> haven't
>> looked
>> into it.
> probably, after all, the 6569 needed +12V for something and the  
> input is very close to the analog output drivers. The 8565 does the  
> same with +5V. That does suggest some changes in that area.

I had a look, and the layout is quite different there (although the  
seems to be mostly the same); things are (relatively) bigger on the 8565
I think.  The 6569 layout is much neater there -- I guess they had to  
everything to fit in the corner, on the 8565.

>> The VIC-II was originally designed for SRAM, not DRAM; it was  
>> obviously
>> not considered at all to do tricky things with RAS/CAS timing ;-)
> If the VIC was originally designed for SRAM then I wonder why they  
> implemented this convoluted address bus (some bits multiplexed,  
> some not) and didn't implement it more straigthforward as they did  
> with TED which supplies normal addresses and uses the multiplexers  
> as the CPU does.

The SRAM VIC (6566 right?) had 14 address pins, A0..A13.  For DRAM there
are extra RAS/CAS signals needed, and all pins were taken, so that left
A0..A11 for address pins, which is no big deal since the high address
signals have to be muxed onto the same pins anyway, for DRAM (either
seven or eight pins, selectable on the metal mask -- you actually have
a double mux per address pin, e.g. that signal selects between A7 and  
and then you mux with A0 depending on RAS/CAS).  All this muxing stuff
sits a bit to the side, not as neatly laid out as the rest, looks tucked
on later (and it is :-) )


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Received on 2011-09-04 17:00:03

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