C65 questions

From: Gábor Lénárt <lgb_at_lgb.hu>
Date: Wed, 6 Oct 2010 09:58:06 +0200
Message-ID: <20101006075806.GA20128@vega.lgb.hu>
Hi All,

I'd like to (try to) write a C65 emulator for myself as a hobby project,
however there are things which are not clear for me even after read some
documents can be found on the Net.  I hope there is someone here who can
answer and suggest some URL about information on the topic.

My problem is about the memory management. You can alter CPU memory mapping
by filling registers A,X,Y,Z then issuing opcode "MAP". Interrupts are
disabled (as far as I know) till the first NOP opcode (which is "redefined"
as EOM - End of Mapping) to avoid problem of getting an IRQ (for example)
before I prepare things, like stack setup.

However this whole issue is a bit mystical for me. For example there is the
integrated CPU port (can be found on C64 too) controllable at address $0000
and $0001.  Those (the data and the data direction registers) are used to
alter the memory layout on C64 and also about the Datasette motor control,
if I remember correctly.  Are those used as a linear (after mapping) address
or CPU address?  That is, if I map some other area for the CPU at the low
memory addresses what will happen if I touch those addresses?  Will they
only work if the linear address (after adding the mapping offset) is
$0000/$0001 or whatever is mapped or not mapped, this I/O port is _always_
at those addresses at the view point of the CPU even if it's not the
beginning of the memory for real (after doing the mapping of the CPU
addresses to the linear addressing)?  The same question about other
situations like accessing non-normal-RAM regions (basic, kernal, I/O,
chargen rom, colour ram).  If I setup to "see" the basic ROM (for example)
what will happen if I map something other memory region with the MAP opcode
before?  I will see the ROM here still, or then it's the RAM based on the
mapping regardless I modified the memory layout according the standard

It's interesting that these mapping (with the MAP opcode) can give me the
ability to set the 8 bank of the 64K address space of the CPU to set to
"non-mapped" (linear address=CPU address). Basically it's the very
same if it's mapped but the offset is set to 0. Then what's the difference?
According to some document I've read, the only difference is that the CPU
has an output signal to show if it's a mapped or non-mapped region. I have the
idea that maybe this signal is used to the create the Chip Enable signal for
various circuits (ROM, I/O ...), so _maybe_ the question I've asked above is
answerable in this way: if the memory layout is set to see ROMs (for
example) you can only see them (at the C64 std location) if the
corresponding CPU address belongs to a bank which is set to non-mapped,
otherwise it will be _always_ RAM regardless of the mapping offset. But is
it true?

What is also unclear for me: how much ROM in the C65 exactly? I've found ROM
images on the net, and they are 131072 bytes long (128K). It sounds a bit
too much for me to have 128K ROM in the C65, and anyway I am not sure how
you can access the parts, if we have C64 compatibility mode on the C65 we
need only a fraction of this size (basic, kernal, chargen ROM) so if C65
uses more ROMs how and where I can access the content, also how can I use
those *.bin files
in the emulator exactly?

Any help is warmly welcomed, sorry for the long mail with possible too much


- Gábor

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Received on 2010-10-06 08:00:12

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