It looks like u4 gate d prevents that. Anding S02 with R/!W prevents OE from being output if RW=0. Am I reading the circuit wrong? On Fri, 1 Oct 2010, Steve Gray wrote: > Hi all, > > Sorry for the delay. I looked at what I'd drawn and realized it was a little > messy, so I've re-drawn it. Please excuse my sloppy drawing skills. I need to > learn one of the layout tools available and make a proper one. > > So, for those interested, here is my hand-drawn CBM-II 24K RAM/EPROM cartridge > schematic: > http://www.6502.org/users/sjgray/computer/cbm2/cbm2-24k-schematic.jpg > > You can see a picture of it on my CBM-II web page: > http://www.6502.org/users/sjgray/computer/cbm2/index.html > > Thanks again to Ernie Chorny for lending me the cartridge!... Ernie, I promise > to get it back to you soon ;-) > > Steve > > > ----- Original Message ---- > > From: "Hoffmann-Vetter, Martin" <firstname.lastname@example.org> > > To: email@example.com > > Sent: Fri, September 24, 2010 7:06:51 PM > > Subject: RE: iec to pet > > > > Hello, > > > > >>> I also reverse engineered the schematics for a 24K RAM cartridge > > >> > > >> I'm always interested in schematics. > > > > > > As am I! > > > > I'm interested, too! > > > > Greetings Martin > > > > > > > > Message was sent through the cbm-hackers mailing list > > > > > Message was sent through the cbm-hackers mailing list > Message was sent through the cbm-hackers mailing listReceived on 2010-10-01 19:00:27
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