Re: visual 6502 simulation...

From: Wolfgang Moser <womo_at_news.trikaliotis.net>
Date: Thu, 16 Sep 2010 11:43:27 +0200
Message-ID: <i6sort$k7d$1@vs5413.trikaliotis.net>
Hi André,

"André Fachat" schrieb:
> 
> In case you haven't noticed, some brilliant guys have analyzed the
> 6502. >From microscopic images of the chip they built a netlist and a
> simulator to actually run the chip, from this netlist!
> 
> http://www.visual6502.org/

wow, thanks for the info. _This_ is great stuff. And my previous boss at
the university, visiting each and every SIGGRAPH, did _not_ inform me
about this!

> This allows to actually analyze all the peculiarities, for example
> why an interrupt during a taken branch is delayed by an instruction.
> http://forum.6502.org/viewtopic.php?t=1634 - might be worth looking
> into that for the Commodore emulators...

And the true nature of _all_ the illegal opcodes can be figured easily
as Michael Steil already did for some here:

	http://www.pagetable.com/?p=39

> I voted for the 6522 as next chip to analyze, to find out about the
> shift register bug. But if you're willing to donate some 6526, they
> might open this one and we finally find out how the timers work....

There are some 20000x20000 shots from the 8726 REU-DMA chip lying around
at my harddisk.... But I thought to save them until I retired ;-)


Womo

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Received on 2010-09-16 10:00:03

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