My primary application was video processing, so the front end would break up a single line of NTSC video analog signal into 1024 discrete samples and send one sample to each processor. Then my entire program had to run, finish, and write its output in real time before the next line started to come in because as soon as a new sample came in each processor was reset and started its execution loop again. I buffered a tiny amount of video to run real-time edge detection algorithms etc across multiple lines, so it was about 8 fields behind real time in total as I recall. The front end would take all the processed outputs and turn it back into a line of NTSC video for display. Each processor had 256k of ram, had no floating point support, and IPC was very expensive cycle-wise. It would scale to 2048 processors, and was air cooled. I burned out a couple CPU's per week because I never shut the machine off, and had to line them out in the config for the front end hardware. Eventually Sarnoff would show up and replace them when enough were bad for it to be worth the trip. You could build your DSP either in a CAD program or by writing code in a weird version of C. To redline the combining-obscure-hardware meter, the development tools ran on an Apollo workstation. Years later when I bought the first Titanium G4 powerbook, I was very entertained by the fact that my 5lb laptop had more horsepower than that 1024 CPU monster. Justin On Apr 22, 2010, at 19:34 , Bil Herd wrote: > At the same time the tools and resources have advanced so much as to make the original hardware/layout rules/netlists obsolete for purposes of PGA's IMHO. Literally a engineer with a laptop can do in a weekend what used to take a couple of months of at least 2 people. The intellectual property would be in the code that that Freddy and others created as true CBM byproduct, again IMHO. > > Sarnoff did REALLY cool stuff and were heavy users of the most expensive Altera's stuff back in the early 90's when I was still doing HW. Not only the HD stuff but things like superimposed billboards on sports games and even some of the subchroma pll's of the day I first saw were from SL notes. Also ended up with some of our good guys like Lengthe and Klautter. I asked an Altera guy who bought the $500 chips and he said SL by the stickload and I pretty much envisioned a board of just raw gateage... your description below p[puts flesh to that vision. > > Bil > > > -----Original Message----- > From: email@example.com [mailto:firstname.lastname@example.org] On Behalf Of Justin > Sent: Thursday, April 22, 2010 6:51 PM > To: email@example.com > Subject: Re: Commodore 65 > > I'm surprised that CAD drawings for the ASICs and whatnot didn't escape along with the death of Commodore. It seems to me they might be just late enough in the game that a series of imports through successive versions of the design software would get you to the point where you could just push it onto an FPGA. I used to program on a massively parallel system designed to do that kind of thing (the Sarnoff Labs "Princeton Engine" used 1024 processors in a SIMD configuration to emulate a DSP). You would design your DSP and then push it over onto the PE and run signals through it to see if it did what it was supposed to, so you could do rapid prototyping of DSPs before going to silicon. Message was sent through the cbm-hackers mailing listReceived on 2010-04-24 18:00:03
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