disable memory refresh of VIC2?

disable memory refresh of VIC2?

From: Michael Huth <enigma_at_mail.lipsia.de>
Date: Tue, 07 Apr 2009 03:10:25 +0200
Message-ID: <49DAA801.3030905@mail.lipsia.de>

a long time ago I had a chat with Graham about RFO and why he did most
of the VDC routines at 1 MHz.
The main problem at 2 MHz is the memory refresh of the VIC that steals
cycles at the end of each rasterline.
Also the clock stretching on I/O accesses might be a problem, but I
think that can be solved.

So then there is the VIC TEST Bit at $d030 that increases the rasterline
counter at each cycle. If this bit is set permanently, does the VIC
still refreshes the memory
or does it leaves the cycles to the CPU?
If there is no more refresh by the VIC the timing would be easier to do.

How does the VIC refreshs the RAM? According to the VIC article it
generates an address and does a write?
Can I do this also via VPU by reading or writing certain addresses?
If yes, what memory addresses are refreshed if I read a certain address?
Only one, $xx00 or $00xx or ....
What access strategy should I implement to do a refresh of a codeblock
in memory?

So can I set 2 MHz, TEST Bit permanently, have a timing without cycle
stealing and do neccessary refresh by CPU accesses?

I know that are alot of question, but anyone knows?


BTW: Wolfgang I got your REU.

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Received on 2009-04-07 03:18:08

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