If you want to send me your schematic when done I can look to see if it matches all of the basic rules.

If someone has the PLA terms for the 82s100 in the 64  (mine are in a box very buried) I can also proof the questions about the different signals by looking at the decode.

25 years ago these different signals were second nature, talk about brain erosion.

Bil Herd



>  3. I'm still concerned about the ROM portion of the layout.  I know
      the address (A13-A0) and data lines, VCC, and GND are correct, but
      I've never laid out a ROM cart.  The A17-A14 lines, the jumpering
      required when one goes from 28 pin JEDEC parts to 32 pin JEDEC
      parts, and whether I can let all the unused address lines float
      high on a smaller EPROM (the extra address lines have other
      functions on smaller EPROMs).  I used Nicholas Welte's EPROM board
      as a guide, but his is not only mapping different size EPROMs, but
      converting them to 23XX/23XXX series layouts, so I'm not sure I
      read his design correctly.
-----Original Message-----
From: owner-cbm-hackers@ling.gu.se [mailto:owner-cbm-hackers@ling.gu.se] On Behalf Of Jim Brain
Sent: Tuesday, March 24, 2009 7:24 PM
To: cbm-hackers@ling.gu.se
Subject: Re: Additional cartridge ROM question

Marko Mäkelä wrote:
> On Tue, Mar 24, 2009 at 12:55:46AM -0500, Jim Brain wrote:
>
>> But, if EXROM and GAME are LOW, but HIRAM and LORAM are low as well, do
>> I get RAM at the two 8K locations, or does EXROM and GAME override any
>> LORAM/HIRAM settings?
>>
> [...]
>
>> The PRG and the various web sites were not helpful in resolving my question.
>>
>
> The PLA equations at
> http://www.zimmers.net/anonftp/pub/cbm/firmware/computers/c64/
> do answer your question.  The shortest equation for CASRAM appears
> in this file, which I haven't checked:
>
> http://www.zimmers.net/anonftp/pub/cbm/firmware/computers/c64/c64pla.txt
>
OK, I plead ignorance at PLA equations.
> I think your question was also answered by the article "Hiding kilobytes"
> that I wrote for C=Hacking #7:
> http://www.ffd2.com/fridge/chacking/c=hacking7.txt
>
It does.  For some reason (probably the hour), I took "LORAM and HIRAM
line" as external cart port lines, and ignored them, as I was looking
for LORAM HIRAM in another part of the matrix (I know, it sounds stupid
at this hour, but I swear it made perfect sense at 1AM or so).

So, from this, I feel comfortable doing 16kB images (though, I left two
jumpers on the board, so an enterprising sort can cut them and have 8kB
image support (they'll lose the top end of each 16kB bank, but SMT
jumpers are easy to add, they were already in the design, so I left them in.

I added a hexadecimal DIP rotary encoder for the highest address lines,
with appropriate pullups.

I think the design is done.  It's at
http://www.jbrain.com/vicug/gallery/nic/ and I'd appreciate any
comments.  Specifically:

   1. The resistor/diode logic that brings /CE low on the 27512 when
      either ROML OR ROMH goes low.  It looks like it's been used on
      other carts
      (http://www.zimmers.net/anonftp/pub/cbm/schematics/cartridges/c64/freezer/MK.gif).
         1. Is 10K for the resistor OK, or should I use 2.2K like the
            Action Replay?
         2. Should I just forego this and put a single AND gate in
            there?  It's $.31 versus $.23, and a few more pins (5 versus 3)
   2. I determined that if another cart was on the bus and brought /ROML
      low, tying ROML directly to the /CE and /OE pins would bring this
      ROM into the address space.  So, I put /ROML on /OE and put /CE on
      a switch to ground.  That way, if the user deselects the /EXROM
      /GAME, the DPDT will also bring /CE high, preventing the ROM from
      appearing in the address space.  Does that approach sound reasonable?
   3. I'm still concerned about the ROM portion of the layout.  I know
      the address (A13-A0) and data lines, VCC, and GND are correct, but
      I've never laid out a ROM cart.  The A17-A14 lines, the jumpering
      required when one goes from 28 pin JEDEC parts to 32 pin JEDEC
      parts, and whether I can let all the unused address lines float
      high on a smaller EPROM (the extra address lines have other
      functions on smaller EPROMs).  I used Nicholas Welte's EPROM board
      as a guide, but his is not only mapping different size EPROMs, but
      converting them to 23XX/23XXX series layouts, so I'm not sure I
      read his design correctly.


Jim

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