RE: How to design non-trivial cartridges for c-64?

From: Bil Herd (
Date: 2007-05-28 15:53:16

Hi Jim,

Well actually there is a different problem when using 65xx family parts
(MOS versions, not later CBM stuff) on the C64 connector/bus.  The 6551
does not use a gated strobe for a chip select, I.E. it sets up any old
time during the addresses, in the 6551 the strobe is the PHI pin.  Look
at the specs and you will see that address, CS and R/W need to set up
prior to PHI going hi and stay stable until after PHI falls.

The problem is that the addresses when PHI rises are actually the VIC
cycle address or invalid as the VIC goes offline and the proc comes
online.  If you were talking to just a 6502 everything would be fine, as
it sets up addresses well in advance of PHI, but the proc in the C64 has
the Address Enable Control (AEC) that toggles and pulls addresses and
R/W out of Hi-Z.

On the Plus4 I had to create a fake Phi2 for the 6551 which would stay
low through the normal low time and then half way through the PHI hi
time it would toggle hi.  Believe I used the falling edge of RAS to cut
the cycle roughly in half, but then I had to make the new fake PHI go
away very fast due to the hold problems mentioned.  I tailored the terms
in the PLA to give best response in this area but I believe that I had
something like a 3 ns timing violation on this chip and that it was the
only known timing violation that we went to production with.




I then had to use a 2mhs part as it effectively had half the time.

Not saying your cartridge doesn't work, I have seen things where they
work depending on what other code is running, things like a bad write
followed by a good one would go unnoticed etc.  check out page 3 of to see the PHI timing


Bil Herd

p.s. You going to VCF East?

-----Original Message-----
From: []
On Behalf Of Jim Brain
Sent: Monday, May 28, 2007 1:15 AM
Subject: Re: How to design non-trivial cartridges for c-64?

Bil Herd wrote:
> If you have an actual example I can maybe comment.
Well, for the Link232 
(, I use a 138

to chop IO banks into 8 segments, but that means the 6551 CS1B is 
delayed by 138's latency, and I normally use LS parts.  I've never heard

of a unit failing to decode incorrectly.


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