Re: How to design non-trivial cartridges for c-64?

From: Ethan Dicks (
Date: 2007-05-22 22:38:33

On 5/22/07, <> wrote:
> I still don't know how to "select", in my circuirty, what memory location my
> cartridge ought to use. What if I want to build a cart that uses memory from
> $deb6 to $deba? And how does the cart "know" when I poke something in these
> memory locations to do something?

Through some combination of '138s or '154s or GALs or CPLDs, etc., you
compare the present value of the address bus on the cartridge port to
some preconceived number (your desired I/O address)... when the Phi/2,
R/W, and other handshaking signals are in the right state _and_ your
comparator circuit matches, the rest of your logic sees that it should
either accept or provide an 8-bit value at the data bus.

Have a look at a schematic for a VIC-20 memoryu cartridge - that's
about as simple as it gets... you'll see that R/W goes right to the
R/W line on the RAM chips, the lower part of the address bus goes to
the address pins on the RAM chips, the data bus goes to the data pins,
Phi/2 goes somewhere (a device select on the RAM chips?), and, since
the VIC-20 partially decodes the upper part of the address bus, there
are memory bank select lines on the cartridge port that go to another
select line on the RAM chip.

The difference between that RAM circuit and what you want to do is
that the C-64 pre-decodes a couple of select lines in the $Dxxx range
(can't remember exactly where off the top of my head), then _your
circuit_ needs to combine that I/O line (since it's affected by
internal bank select stuff in the 82S100 PLA) with the lower bits of
the address bus to create a single select per I/O chip to tell it that
the desired address has been selected.

Most people just use the $Dxxx select line on the port because they
don't care that 256 addresses will trigger that line.  If you have,
say, a 6526 that you want to add to the cartridge I/O space, you would
hook A0 on the cartridge port to A0 on the 6526, A1 to A1, and so on,
but then you will see several copies of that same chip at "mirror"
addresses.  By comparing or decoding, say, A7-A4 (or whatever) to some
pre-existing value, either with an "address comparator chip" (used
commonly with older ISA boards) or a device selector chip (74ls138 is
a 3-line decoder, a 74ls154 is a 4-line decoder where the "n-lines"
are how many address bits they can decode), then using logic gates (or
replace the whole thing with a GAL), you combine the page-granularity
$Dxxx line with the address lines from the cartridge port to eliminate
the mirror copies of your peripheral.

Hopefully this sheds some light on what I think you are trying to do.
If you don't know what a 74LS138 or 74LS154 does, it might be useful
to find a book on TTL or CMOS logic circuits and see how NANDs and ORs
and such combine into larger functions.  A lot of this stuff hasn't
been in use with new equipment for a lot of years, so you may need to
find some books or tutorials from the mid 1970s through the late
1980s.  Don Lancaster's "TTL Cookbook" and "CMOS Cookbook" are
excellent resources if you can find copies online or at your library.


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