From: Jim Brain (brain_at_jbrain.com)
Date: 2007-04-09 06:37:14
Scott McDonnell wrote: > Yeah, data sheet says VCC/2 or 2.5V, but I believe your real-world > testing more than the datasheet. > > Definitely 256 clock cycles shouldn't be needed to discharge the cap if > it is shorting it to ground, but they are used anyway for whatever > reason the engineers decided to do it that way (reusing the same timer, > maybe?) Now, this is something I am NOT familiar with but are the > You must have missed my theory in the last post: "The thrifty rationale is how I explain the 512 cycle period. Since it would have taken 2-5uS to completely discharge the cap, they'd need to wait that long (or a bit longer) before unclamping the line and starting the counter. That would mean another counter, or a check of 261 (256 line + 5 or so) on the counter (more gates), and then more gates to reset the counter. Since the POT lines were assumed to be DC (no periodic waveforms), letting the counter simply roll over used the least gates for the task at hand. " > contents of the counter available while it is running, or is it latched > into a register after the 512 cycles are up? If it is available to read > while free running, this would definitely increase the usefulness. > The counter is not visible, just the registers. That's why I'm theorizing about the 9 bit counter, but it makes perfect sense. Use the high bit to clamp the inputs, and use a comparator to latch the counter value into the SID register. It's a shame all of this good info isn't of current help to the original poster. Jim -- Jim Brain, Brain Innovations (X) firstname.lastname@example.org Dabbling in WWW, Embedded Systems, Old CBM computers, and Good Times! Home: http://www.jbrain.com Message was sent through the cbm-hackers mailing list
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