Re: Nested interrupts in a 15x1

From: Marko Mäkelä (
Date: 2006-12-18 10:17:24

On Mon, Dec 18, 2006 at 10:01:47AM +0100, wrote:
> AFAIK there are no nested interrupts in a 1541.

What do you mean with nested interrupts, Ruud?  I once measured the
interrupt processing delay on the 6510, but I believe that the results
are valid for any NMOS 65xx processor.

If my memory from about 10 years ago is correct, if an IRQ occurs during
the first two cycles of a BRK instruction, the BRK instruction will mutate
into the IRQ.  I cannot remember what happened when an NMI interrupted an
IRQ, but I'd guess that the NMI would take precedence.  Because the NMI
probably sets the Interrupt flag, the IRQ would be processed right after
the RTI (which typically clears the flag) at the end of the NMI handler.


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