From: MagerValp (MagerValp_at_cling.gu.se)
Date: 2005-10-13 18:57:13
>>>>> "MM" == Marko Mäkelä <marko.makela@hut.fi> writes:
MM> Are you absolutely positive that the memory corruption is because
MM> of lacking memory refresh? I always thought it is because of a bus
MM> glitch, i.e., the VIC-II would start DMA immediately upon
MM> receiving the write to $d011, while the 6510 is still holding the
MM> R/-W line low.
MM> According to my measurements, the built-in memory refresh in the
MM> VIC-II, VIC-IIe and TED simply access some memory locations. On
MM> the VIC-II and VIC-IIe, the locations are $3fff to $3f00 in the
MM> currently selected 16k video bank, five addresses per line, in
MM> descending order. The VIC-IIe and the TED will switch to "1 MHz
MM> mode" during the memory refresh cycles.
Oliver Achten, designer of the MMC64, has made a device that renders
the C64 bus access as video. The ram refresh accesses are clearly
visible as fading green lines, and when certain $d011 effects are
used, you can see the ram refreshes being interrupted. I'm afraid I
don't have the link to the screenshot anymore, and Oliver is not on
the cbm-hackers list, but I've Cc:d him here.
--
___ . . . . . + . . o
_|___|_ + . + . + . Per Olofsson, arkadspelare
o-o . . . o + MagerValp@cling.gu.se
- + + . http://www.cling.gu.se/~cl3polof/
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