From: Spiro Trikaliotis (ml-cbmhackers_at_trikaliotis.net)
Date: 2005-10-12 18:09:24
Hello,
On Mon, Oct 10, 2005 at 08:24:37PM +0200, Gideon Zweijtzer wrote:
> Since the VIC chip generates the refresh cycles by actually counting
> through the rows, only 2^8 of all rows will be refreshed on the SIMM.
> In addition to the multiplexing of the additional row/column bits, you
> need to make a distinction also between an access and a refresh cycle.
Does the VIC even use special refresh cycles?
According to some data sheets I have here, the refresh ("RAS only
refresh") can be done simply by accessing a specific row. No need for
CAS. If you access all rows, all rows are refreshed.
Now, the interesting part is: If you do not issue a special refresh
cycle, but just access some data in a row, that row gets refreshed too,
as RAS is set, thus, the row goes into the output buffers, and RAS is
deasserted again later, thus, the row goes back where it belongs.
I always thought the VIC refreshed the DRAM simply by accessing it. If
you "swap" A0-A7 and A8-15 inside of the VIC, the VIC just accesses
every row while generating its screen ($0400-$07E7), as the last byte
cycles through all possible values. Thus, it could refresh all 64 KB RAM
just by displaying the screen.
Is this wrong? Does the VIC really generate some refresh cycles?
Regards,
Spiro.
--
Spiro R. Trikaliotis
http://www.trikaliotis.net/
http://cbm4win.sf.net/
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