6502 Clock issues

From: fachat (afachat_at_gmx.de)
Date: 2005-05-17 17:45:44


after the earlier discussion on how to handle "page faults"
on a 6502, I investigated a bit further. We basically concluded
that the 6502 can only be haltet, during the paging, but not
do the paging itself due to the missing capabilities to restore
register values in the 6502. Therefore I investigated two-CPU
systems. I found some interesting details:

I) On two-processor machines:

1) SuperPET
The SuperPET has a 6502 and an 6809 CPU, which both use the same
electrical and logical bus design. To switch from 6502 to 6809,
the 6502 is simply "switched off". I.e. Vcc is cut off. for this
purpose the 6502 has an own voltage regulator.
Another interesting fact is that Phi2 is not used as produced
by the 6502, but instead created externally. For this purpose the
Phi0 input is latched with the 16MHz base clock, thus giving a
delay of up to 31.5 ns.

2) 4040 dual disk drive
The disk drives have a 6502 and a 6504 (6502 with reduced address
range). One CPU gets the inverted Phi0 of the other as clock input.
So both CPUs run in parallel using each one half-cylce of the original
clock. The address lines of the shared memory are multiplexed between
the two CPUs using the clock line signals.
Interestingly the data bus of both CPUs is directly connected, which
means that the data bus is in fact really needed a short time only
(or in the respective half-cycle only). 

3) C128
The C128 is the most sophisticated system in that it allows to 
dynamically change the CPU that is using the bus. In addition it 
must cope with the 2MHz/1MHz differences when accessing the I/O
Here two mechanisms are used:
 a) When the 6502 gives control over to the Z80, as well as when the
 VIC needs a DMA access to the memory, the RDY line signals the CPU 
 to stop. It does this in the first read cycle after finishing all 
 write cycles, which might be up to three. But this matters only
 when the DMA interrupts the CPU, in the other cases, this can be
 programmatically handled (not to write when the Z80 gets control).
 b) When the CPU is in 2MHz mode and has to access the I/O, that
 runs in 1MHz, the clock input to the CPU is "stretched" from 
 one 2MHz to 1MHz.
Interestingly in this system the system Phi2 is not generated by the
CPU, but also by the VIC.


In general there are three things to note:
1) The Phi2 can be created externally and the system still works
2) The 6502 CPU can be stopped for extended amounts of time with RDY,
   but has to wait for write cycles to complete
3) The 6502 CPU can be slowed down by cycle stretching

II) On 6502 types
Now to investigate what possibilities there are to implement a 
"page fault" handling system with the 6502 I had a look at the 6502
data sheets:

1) NMOS 6502
This CPU can be stopped using the RDY signal. However, write accesses
are not stopped. So when a page fault occurs during a write operation,
this must be handled specially (piping the writes - data+address -
in a fifo and handling them one-by-one)

As for slowing down the CPU, the specs say that there is a "minimum 
clock frequency of 50kHz" resp. a maximum cycle time of 10us.
Therefore the CPU can not be stopped for long using the cycle stretch

2) R65C02
The CPU can be stopped with the RDY signal. And as opposed to the NMOS
6502 above, the write cylces are stopped too. 

As for slowing down the CPU with cycle stretching, there also is a 
maximum time for Phi2-low. However, the specs say that "the CPU can
be halted with Phi2 high".

III) 6502 with "page fault handler"
So to implement the 6502 with a page fault handler, there is only
the option to use the 65C02, and the RDY signal. Using the clock
stretching method, then the pager would not have enough time to page
in the memory. Using the NMOS 6502, there would be an enormous effort
to handle the writes that are not stopped with RDY. Therefore, only
65C02 and RDY signal.

How would this be implemented? Assume that at a page fault the main 
CPU is halted, and the memory is paged in by an auxiliary (6502) CPU.
Starting from a 6502 that uses an MMU to expand some (upper) address
lines (e.g. my CS/A65 with the 74LS610 MMU), these are the changes 
that would be needed:

1) The MMU needs an additional output (or a special page number could
be used) to signal that the memory addressed by the CPU is not mapped.
2) The "CPU selection" circuitry must detect this situation, and
   a) pull down the RDY line on the orignal CPU and
   b) release the RDY line on the auxiliary CPU  
3) The Aux CPU must be able to read the main CPU address to determine
the faulted address. Here some I/O port must be implemented for the 
Aux CPU to read the address lines
4) The Aux CPU must have access to the main memory, to page in the
required data (and to possibly read the information prepared by
the main CPU where to read the data from)
5) The Aux CPU must have access to the MMU registers to change the
mapping of the faulted page to an existing page
6) The Aux CPU must be somehow able to give up control and tell the
CPU selection circuitry to stop itself and continue with the execution
of the main CPU. 
7) In case there is an error (e.g. the memory could not be paged in),
the Aux CPU must be able to set an interrupt (NMI) condition on the 
main CPU that this CPU must use to kill the faulted process.

What do you think, would that work?


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