From: Greg King (gngking_at_erols.com)
Date: 2005-04-30 04:12:19
From: Jim Brain; on Date: April 27, 2005, at 12:50 AM -0400 > > I think if you lag 6 cycles, you're guaranteed to lag enough, but you > have the opposite issue, in that you might not be just 1 op off. > > If you execute a 6,3,4,6, and the page boundary is on the first cycle of > the last 6 cycle opcode, the lagged cpu is just finishing the 3 cycle > op, and has not started the 4 cycle op, so the state of the lagged cpu > is too far behind. There is another problem with that scheme: Memory increments/decrements can destroy the processor syncronization. When the slave CPU executes the inc/dec op-code, the memory target will have a different value. So, the slave processor's flags might be different from the master's flags (think about what would happen if a location had $01 in it, and the instruction decremented that location)! Message was sent through the cbm-hackers mailing list
Archive generated by hypermail pre-2.1.8.