From: Jim Brain (brain_at_jbrain.com)
Date: 2005-04-27 06:17:53
john/lori wrote: > I imagine getting the internal stuff via an ISR meaning you'd need to > generate that IRQ in such away that the slave had finished the last good > instruction, but the bad instruction hasn't done any damage. > Last good instruction might take 6 (7?) cycles before it updated the > internals. I was basing that off the REC IC's behavior of waiting 3 cycles after BA asserted to take the bus. But, if you want the current instruction to finish, you are correct, you'd need to wait 6 cycles. I think if you lag 6 cycles, you're guaranteed to lag enough, but you have the opposite issue, in that you might not be just 1 op off. If you execute a 6,3,4,6, and the page boundary is on the first cycle of the last 6 cycle opcode, the lagged cpu is just finishing the 3 cycle op, and has not started the 4 cycle op, so the state of the lagged cpu is too far behind. The only thing I think of doing is to stretch the cycle during a page fault to the maximum allowed and use another processor to do something during the time you have. Or, if the processor is static, simply stop the CPU and use another to map the page in. Jim -- Jim Brain, Brain Innovations firstname.lastname@example.org http://www.jbrain.com Dabbling in WWW, Embedded Systems, Old CBM computers, and Good Times! Message was sent through the cbm-hackers mailing list
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