Re: Question about writing to 1541

From: fachat (
Date: 2005-04-25 00:24:15

On Sat, Apr 23, 2005 at 11:42:59AM +0200, Spiro Trikaliotis wrote:
> Thus, if we execute the statements (taken from the DOS ROM routine)
> .8:f5bf   B1 30      LDA ($30),Y  ; write the last bytes
> .8:f5c1   50 FE      BVC $F5C1
> .8:f5c3   B8         CLV
> .8:f5c4   8D 01 1C   STA $1C01
> then $F5C1 waits until the load for the PREVIOUS byte has been executed.
> With STA $1C01, we give the data byte for the next round.

AFAIR this is true. The LD input of the shift register is "almost"
the same as the BYTE READY signal. So when the byte is ready, which
is signaled to the CPU via SO, the shift register is loaded with
the value from VIA PA. After that a) the shift register starts
shifting out the new value, and b) the CPU knows that the new value
has been taken and that it can change the value of VIA PA ($1c01).
I.e. if you roll out the loop, you get

     CPU                      register
     SO                       load "PREVIOUS" data from $1c01
    F5C1 continues            start shifting out "PREVIOUS"
    F5C3 CLV
    F5C4 STA $1c01 (store "CURRENT")
    ... increase index
    F5BF LDA ($30),y
    F5C1 wait for PREVIOUS Byte Ready
                              shift register finishes "PREVIOUS" byte
     SO                       load "CURRENT" data from $1c01
    F5C1 continues            start shifting out "CURRENT"
    F5C3 CLV
    F5C4 STA $1c01


In short (if N bytes are to be written):

	write byte N-1
	wait for byte N-2 to finish
	write byte N
 	wait for byte N-1 to finish
	wait for byte N to finish

However, when the CPU gets the signal that the Nth byte
is written shift register already starts to write the 
Nth byte again! When the CPU then comes to switch to read
mode, part of the second write of the Nth byte is already

Don't have the ROM listing here, so I cannot comment on the
number of bytes written on a format or on a block write.
maybe later.

So long

P.S: I didn't CC: anyone :-)

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