From: Gabor Lenart (lgb_at_lgb.hu)
Date: 2005-04-01 13:54:39
On Fri, Apr 01, 2005 at 01:00:34PM +0200, Ullrich von Bassewitz wrote: > STZ was an additional instruction for the 65SC02, 65C02 and 65816 CPUs, and it > is officially documented as "Store Zero". > > When the 65CE02 came along, Commodore implemented a Z register and redefined > STZ for this CPU to mean "Store Z register". But the 65CE02 is a very rare CPU > (it was used in the C65), and was never officially available for sale. So in > my eyes it would by confusing to use this "Z register notation" when talking > about the 65SC02, 65C02 and 65816 CPUs. Exactly, however some years ago I've done a little summary on 65xx CPUs just for myself, and when we're talking comparsion about the CPUs in this family (eg in a table) it's easy and logical to assume that Z is register Z which is a contanst zero "source", but it's modifiable on 65CE02. However this is not true if we're doing the comparsion based on timeline. Since I'm not familiar with the internal implementation of the CPU itself I can't say that implementation of STZ (in the notion as store zero) is similar to STZ (in notion as store register Z) inside 65CE02, I mean store zero has got totally different internal implementation compared to store register X, or similar (just using some "dummy" register source, eg grounded lines instead of the output of the register "block" itself). So I think it's pointless to argue on this topic ... - Gábor Message was sent through the cbm-hackers mailing list
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