William Levak wrote: > Read and write to PET video memory is crontrolled by an interrupt > generated by the clock on one of the interface chips. This same signal > (among others) is used to controll screen memory read by the display > circuitry. This signal separates read and write of screen memory so that > basic can only access screen memory on it's half of each cycle and the > display circuitry accesses it the other half (thirty times per second). Ok, now I get what you mean. It's the vertical retrace input that says the CPU when the video logic does not access video memory. > > It is possible to disable this interrupt and speed up the PET. However, > when this is done, it results in "snow" on the screen. Simply put, the > cirtuitry is not quite as fast as the numbers say it should be, and it is > necessary to resort to this scheme to produce an acceptable display. Yes, this method is possible. But all PET boards but the very first one have this fixed. The very first PET boards had a slow video memory, so either the CPU or the video could access the memory, but not both in one cycle. Accessing video memory by the CPU when the video reads its data then sends wrong video data to the screen - "snow". But all but the first PET computers have this fixed (i.e. they ahve faster video RAM that allows interlaced - Phi1-video/Phi2-CPU - access). Andre -- Email address may be invalid. Use "fachat AT physik DOT tu-chemnitz DOT de" ------Fight SPAM - join CAUCE http://www.cauce.org------Thanks, spammers... Andre Fachat, Institute of physics, Technische Universitšt Chemnitz, FRG http://www.tu-chemnitz.de/~fachat - This message was sent through the cbm-hackers mailing list. To unsubscribe: echo unsubscribe | mail email@example.com.
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