Re: SFD-1001 (8[02]50) diagnostic codes ?

From: Andre Fachat (
Date: 1998-05-07 02:28:27

Marko Mäkelä wrote:
> BTW, I got new PET schematics: the SuperPET add-on boards and the new
> universal system board.

The PET 8032 schemtics are nice, esp. as they now prove some assumptions
done with teh reverse-engineered schematics.

For example "vertical drive", the CRTC vertical sync output is connected
to VIA PB5 and PIA CB1, generating the system interrupt. Interestingly
the CRTC output is inverted by an XOR, if the other input of the XOR is
set. This input is jumpered to ground in the "normal" 8032 schematics by
default, open in the "univ" board and to 5V in the univ2 board...

Also they show how to upgrade a 4032 with CRTC (fat 40) to an 8032.

Unfortunately they are all schematics for the "#3" board in my index,
i.e. for the 12" models in the edgy case, not the new one (the rounded
case like the CBM-II High-profile) as well as 8296.

So we still need to schematics for the 8096 64k expansion board and
the 8296 board with 128k RAM.

For teh SuperPET I only had a look at the combined schematics.
Do you know how they did it? They simply removed the 6502 by the expansion
board - actually connected by a cable! - Ruud, like your BigPET project :-)
Both CPUs, the 6502 and the 6809 have the same bus interface
(nice historical reasons, if someone wants to elaborate... :-)
So the busses are actually directly connected. 
Guess how they switched off the 6502 when the 6809 was active? 
They switch off Vcc to the 6502!

The E output of the 6809 (similar to Phi2) is used as the 6502s Phi0
input, leaving Phi1 and Phi2 outputs of the 6502 open!

Writing to $EFFC stores the byte value in a register that is used 
for some address decoding...
$Eff8 is a system latch that for example can pull down the diag pin...
If I interpret that correctly, if jumpered to 6502 the system latch
can enable switch between the CPUs. Switching back to 6502
would do a reset, as the Vcc had been down, and with DIAG it was probably
possible to do some non-standard init (with a new ROM?)
Also the RAM in $9*** can be write-protected.
Both seem to be accessible from both CPUs. Actually the 6551 seems
so too. (Although I have to figure out the address... 
6551 should be at $EFF8-$EffB (4 registers))

Harhar. They do real dirty tricks... Ever wondered why the 8032
schematics has a connection to the CPU pin 5 or 36? They are not
connected in the 6502, but they are on the SuperPET expansion board.
The /NOROM line mirrors the 6809/6502 jumper and disables the 
motherboards ROM selection...
However, the univ2 board has the /NOROM at pin 5 of the 6502, the 9000016
SuperCPU schematics have them at pin36...
Only if the motherboard ROMs are disabled (6809 mode), the SuperPET ROMs
are enabled. 
This is probably also used for the 8096 64k RAM expansion board!!
(With this input it's actually pretty simple..., kind of drawing practice...)

It seems the 64k RAM are mapped in $9***, with the bank switch register
providing the upper 4 address lines.

However, I have _no_ idea what the 6702 does. 
If, any only if those chip select line descriptions are right, it is
mapped at $EFF0-$EFF3. As it does have no connection to A0-1, all four
addresses are the same. It is, however, connected to the dynamic
RAM data bus, not the CPU bus.
If the address range $EFe* (e = even digit) is selected, then the 
RAM data bus is connected through to the CPU data bus, probably for
access to this register. The select line for this area is called "KIO"?
So who knows?

Writing to $EFFE stores the data bit0 and switched between ROM (1) and 
RAM (0) in $9***. This is only one special ROM socket - does the 
PET have an autostart test for an autostart sequence in $9*** when
diag pin is set? This would nicely fit with switching the CPUs...

So far for the preliminary diagnostics...


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Andre Fachat, Institute of physics, Technische Universität Chemnitz, FRG

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