Hallo allemaal,
The first partof this email is my RE on Andres RE on 74LS612. But it
contains two interesting parts marked by ===== concerning clocking ICs.
The second part replies to other emails.
Hallo Andre,
> added by the user. Another difference is that the behaviour of the MMU is
> preprogrammed in the factory and cannot be changed. But with the 612 the
> user can program its behaviour any time. Speaking in MMU-terms this would
> mean that we could program the MMU in such away that BANK 0 behaves like
> BANK 3, BANK 3 and 1 as 1 and BANK 2 as 1 as well.
>What does that mean? I don't get the point here.
I tried to explain that you even can change the order pages appear. If even
you didn't understand it, I missed my goal :-( See second version.
> If I find it again and you like it I can dig out an old tex graphics I >
produced to show how I used the '610 in my CS/A65.......
Please do.
> You should probably now define the terms "virtual memory" and "real
> memory", with the CPU (virtual) memory address range going from 0-64k and
> real from $000000 to $ffffff.
IMO for hardware virtual memory is memory which actualy is harddiskspace
because the machine has not sufficient RAM. The Mainframe boys here
confirmed this statement. But they said that for software it is virtual
memory as well. Confusing IMO.
>> MM Map Mode input. When (H), MO0/MO3 reflect MA0/MA3,
> ^ uhm, I think I once fell for this bug too. AFAIR it's
> reflected at MO8-11, not MO0-3. Then MO0-7 would be low.
You are absolutely right.
===========================================================================
>> for this problem is to disable Clock2 towards the original system....
> Outch. I am not really sure about that. This would disable all timers,
> make some of the chips (I think, the ones that are not static devices and
> have a minimum clock frequency specified) loose memory.
You really know how to spoil someones fun :-( This remark has an extra
impact because I'm building a IC-tester. This simply would mean that some
devices cannot be tested unless you provide a clock in some way.
This triggered the next thought: I once tried to run a 6502 on a clock as
low as possible. It run on 500 KHz. I'm not sure if it still run at 250 KHz
but it failed to run on a lower frequncy anyway. The reason to build
dynamic RAMs is that it saves space but for those few registers in a 6502
or other IC..... AFAIK the Z80 even can be clocked by hand if you want to.
So if someone can tell me more of the background of this "dynamic"
behaviour, I would be pleased.
BTW, which ones are static and which ones not?
==========================================================================
> the r/w line was driven high to the original system (read).
> This is not perfect, however. In fact you would have to make the
> address lines show a "safe" address to the original system......
That was what I had first in mind before I got that "great" idea. Address
$0000 is the most safest address for the C64/128 but this would mean using
extra ICs (541). (I don't like using "pull down" resistors, 3K9 or lower,
as they stress the bus to much) The next safe address is $FFFF; then you
only need some 33K pull-up-resistors.
==========================================================================
>> Andre Fachat built a 4 MHz 65C02 based computer, ......
> Uh. It's running at 2MHz, but needs a 4MHz CPU to meet the timing.
> The 4MHz has earlier address line outputs, which makes MMU mapping
> at 2Mhz possible. There _is_ some delay in the MMU (plus drivers, plus
> bus delays safety margins, plus memory decoder delays...)!
I remembered an email where Frank mentioned that the reason a 6522 cannot
be connected to a 6510 straight away was that the 6522 expected a valid
address at the rise of CLK2. The difference between CLK0 and CLK2 are only
6 ns. The VIC20 uses a 74LS04 to generate a signal out of CLK0 that enables
the 245s between the addressbus of the 6502 and the rest of the bus. This
means that the addresbus will be valid "a long time" AFTER the positive
edge (I think plm. 20 ns.). This is in conflict with the above.
As I said earlier, I have no problems using my 65816 in my 8032, in an
Acorn Atom and, since yesterday, in my 3032. But if I replace the 6502 of
my VIC with my 65816 circuit: nothing :-(. Technical information: I
generate CLK2 out of CLK0 by sending this signal through two cascaded
74F04s. The only thing I can think of is that for one or another reason
CLK2 is delayed too long for the VIC-chip.
Then your problem Andre, why not delaying the positive flank of CLK2 with
this idea:
|-----\
| \
CLK2 ---------------------------------------| \
| | >------CLK2'
| |\ |\ |\ |\ | /
|--| >O----| >O----| >O----| >O----| /
|/ |/ |/ |/ |-----/
AND-gate
OK, you shorten the positive half of CLK2 but not that much that it will
japardize the 6522 and other ICs.
Gentlemen, your opinion please....
===========================================================================
> NO!!! The latch is used! ....... meaning that the MMU is suddenly
> deselected again.
You're right about that. But that is what I call reprogramming it on the
fly. In my unfinnished design I have the possebilty to set MM again meaning
MO8/11 reflect MA0/3 whatever the state of CS is.
>> 4) Why do you use 245s instead of the more power friendly 541?
> Because I didn't know about the 541. Do they also have the same
> solder-friendly pinout (sometimes I even use '245 for uni-directional
> drivers because of that)?
Yes, they behave like a 245 configured as A -> B ie. DIR = (H). You use the 245
in the B -> A mode and replacing them with a 541 would cost a lot of work. But
it is good to know they exist. (I didn't know about the 641, remember...)
>> At the moment I'm working out an idea of combining a 65816 and a
>> 74LS610.
> I wonder if this is necessary. Esp. as the '610 is not really fast,
> and when you want to have the 65816 running at speed....
But the 65816 does not have the capability to shuffle the complete
memorymap and that's what I want most; remember my email saying I prefer
the 612 above the 65816. The reason of adding the 65816 to the design is
the fact that I got it working on the 8032. If I should run into troubles,
I only have to replace one jumper (and the uP of course).
> I was thinking about using a 65816 at 8 MHz, with (Ah, I love those new
> RAM chips...) _one_ 512k static RAM chip (expensive, but so what... :-)
I only have 5 Mhz. types. What does a 65816 cost anyway?
==========================================================================
Prices in US or where ever please?
==========================================================================
> It would indeed not be possible to do those nice mapping tricks with this
> setup, but I don't want to use it for that anyway.
> It might, however, be useful to map slower I/O stuff around when you are
> more interested in speeding up/debugging original 8032/VIC20 or even
> C64 programs. But remember, the delay in the MMU is not neglectable,
> esp. when running with higher speeds.
And now I tell you my (IMHO) genious trick: as long as you use bank 0,
($000000/$00FFFF), the 612 is working. Any other bank and the 612 is out of
function. In this way I can mix both functionalities and using the 65816s
full speed.
>> I do have the SCHs of the B-machines (Service Manual B Model
>> Computer, Jan. 1985) including parts list: 68B45, no 6567. Would also
>> meam a complete different design IMHO.
> Is it the same as on funet? It has a 6845 too, if I remember correctly.
Looking at it description it appears to be the same.
But I have to withdraw my remark as solid proof never can beat humble
opinions.
(Network)
> Yes, that's exactly the point where I'm stuck too.
> I haven't found any appropriate driver.
> RS485 cannot allow collisions, and simple open collector might be
> not reliable enough.
Why not, using a HS-transistor or FET could do the trick.
==========================================================================
Hallo Ethan,
>> Very nice. (I always used the 8250 and 16450 with 65xx-systems)
> Are there any odd interfacing issues? (R/W vs /IOR and /IOW kinds of
> stuff)
No. I connected a 8250 to my C64 only using one 74LS139. This IC exists of
two 2-4 demultiplexers. One I used for deriving the right IOR and IOW
signal, the other one as inverter for the RESET signal. IO1 was used for
the CS-signal and the first demux as well.
> I'd have to check the 75176 data sheets (it's made by.....
Please do.
Hallo John,
> Unless you're doing really stupid things (like putting mains voltages on
> the data lines), you can't damage the drivers........
> .....Just remember that RS485 likes to see a simple cable with devices
> hanging off it, and a terminator at each end. No branches, and
> definitely no loops.
Looks very promising. Unless there are better ideas, we can focus on this
IC.
Hallo Marko,
> I have the UltiMax schematic diagram on paper, but I would need at
> least a 2000dpi grayscale scanner to make it readable, it is an extremely
> bad copy. If someone (Ruud, I'm thinking of you :-) offers to
> reconstruct the UltiMax schematic, I can mail a paper copy (one DIN A3
> sheet I think) to him.
Ruud Baltissen
Italielaan 82
6414 TR Heerlen
The Netherlands
Hallo Andre,
Second version
---------------------------------------------------------------------------
74LS612
The 612 is an MMU, Memory Management Unit, that enables you to expand your
system with 8 extra addresslines. Notify the fact that I use the word
"system" and NOT processor. The processor won't be aware of those extra
addresslines. In case of the 6502/6510 the processor still only can address
64 KB.
What does a MMU?
If you own a C64 or C128 then this is easy to understand. Both machines
have at least 64 KB of RAM, 4 KB of I/O and at least 20 KB of ROM. But the
6510 and 8502 have only a 16 bits addressbus capable of only 64 KB. How do
these numbers match? A more experienced programmer knows that he can read
the contents of the RAM "under" the BASIC-ROM but has no access to the ROM
at all at that moment. It is either RAM or ROM but not both! The same
situation occurs with the I/O, CHARROM and the under laying RAM: it is
either this or that but not all (or in this case not even two out of
three). The C128 has 128 KB of RAM but if we want to read the contents of
address $3887 in Bank 1, we are not able to read the contents of the same
address in the other RAM-bank, Bank 0.
The PLAs and the 128MMU give the C64 and C128 the ability to handle more
memory then the processor is capable of, but not simutaniously.
How do these 8 extra addresslines fit in the system?
The C128 has 128 KB of RAM, 4 KB of I/O and a lot of ROM. If everything had
to be connected to a regular addressbus, we at least needed two extra
addresslines. And the C128 does not have these lines. Or does it?
Yes, it does have these addreslines but we either don't have access to them
or we don't recognise them. In case of the 128MMU they are inside the the
MMU itself. In case of the PLA the outputs of the onboard port of the
6510/8502 function as the extra addresslines. In other words, this means
that the user/software controls the state of these extra lines by means of
one or more registers and not the processor.
The 612 outputs twelf addresslines of which four (can) reflect the state of
four originally attached addresslines. The PLA and 128MMU only output
ChipSelect-lines. This is one of the two major differences between the 612
and these two C= ICs: they have onboard decoders.
The 74LS612 does not have these decoders. This means it provides the
_address lines_ like the original CPU, only more of them and nothing else.
The decoders that translate the address to the chip select lines must be
added by the user. Another major difference is that the behaviour of the
128MMU and PLA have been preprogrammed in the factory and cannot be
changed. But with the 612 the user can (re)program its behaviour any time.
The 612 has 16 registers of 12 bits each. The normal procedure is to
address these registers by four addresslines. Four bits of the output are
used to replace the original four addresslines, the other eight bits to
form the extra eight addresslines. Every bit can be programmed as the user
whishes meaning that the four bits reflecting the original addresslines can
have differ with them. Reconfiguring the original addresslines gives you
the possebility to re-arange the internal configuration of the whole
memorymap. By example in a C64 you could swap the the range $6000/$7FFF and
$E000/$FFFF to test a new Kernal-ROM.
####### Text graphic of Andre
The extra eight lines can be used to add extra memory (RAM, ROM) or I/O in
any way you want. A very nice example is to connect a complete 1541 to your
own system by means of a small interface which replaces the original 6502.
This interface is addressable from $01000 to $01FFFF. Now you can
reconfigure your own system in such a way that the 6502 sees the range
$010000/$01BFFF of the 1541 on its own $0000/$BFFF and the area
$006000/$009FFF as area $C000/$FFFF. In this way you comfortably can test a
new Kernal for the 1541.
Pinouts.
+---------------------+
RS2 -+ 1 40 +- +5V
| |
MA3 -+ 2 39 +- MA2
| |
RS3 -+ 3 38 +- RS1
| |
/CS -+ 4 37 +- MA1
| |
/STROBE -+ 5 36 +- RS0
| |
R/W -+ 6 35 +- MA0
| |
D0 -+ 7 34 +- D11
| |
D1 -+ 8 33 +- D10
| |
D2 -+ 9 32 +- D9
| |
D3 -+ 10 31 +- D8
| 74LS612 |
D4 -+ 11 30 +- D7
| |
D5 -+ 12 29 +- D6
| |
MM -+ 13 28 +- NC / C (see text)
| |
MO0 -+ 14 27 +- MO11
| |
MO1 -+ 15 26 +- MO10
| |
MO2 -+ 16 25 +- MO9
| |
MO3 -+ 17 24 +- MO8
| |
MO4 -+ 18 23 +- MO7
| |
MO5 -+ 19 22 +- MO6
| |
GND -+ 20 21 +- /ME
| |
+---------------------+
Pin functions:
D0 thru D11 Connection to the databus when programming the registers
RS0 thru RS3 Connection to the addressbus when programming the
registers, normally A0 thru A3
R/W Read, active (H) and Write, active (L)
STROBE input to enter data into choosen register, active (L)
CS ChipSelect, active (L)
MA0 thru MA3 connection to the addressbus during normal operation
MO0 thru MO11 The generated addresslines
MM Map Mode input. When (H), MO0/MO3 reflect MA8/MA11,
MO0/MO7 are (L). When (L), MO0/MO11 reflect the 12 bits
of the choosen register.
ME When (H), MO0/MO11 are tristate else active.
NC Not connected.
74LS610, 74LS611 and 74LS613.
The 610 is an 612 plus an extra 12 bits latch. With the 612 MO0/MO11 always
react on the behaviour of MA0/MA3 and MM. With the 610 you can freeze the
output as long as you want. This is archieved with an extra inputline at
pin 28, C (= Clock). A (H) on this input will the 610 behave like a 612, a
(L) freezes the configuration.
The 611 and 613 are the Open Collector versions of the 610 and 612.
The 12 bits registers of the 74LS612.
The intention is to use the 612 in combination with a 6502 based Commodore
and as you know these are all 8-bitters. This means we either have to
disregard 4 bits or use a trick to be able to use all 12 bits. In the first
case we are still able to address up to 1 MB of memory or I/O. If you still
want have those extra 4 bits then a simple 74LS373 will do. Of course
you'll need a decoder for this 373 but as you need one for the 612 as well,
it won't be that much difficult to combine them into one decoder.
Connecting the 612 to a 6502.
Connecting a 612 to a 6502 can be split up in two parts anyway: the memory-
part and the I/O-part.
Memory-part.
If you only want to reconfigure your system within its own 64 KB, then you
only have to "cut" the addresslines A12 thru A15 and to place the 612 in
the created gap. Practically this probably means you replace the processor
by a small circuitboard with onboard the original processor, the 612 and
some logic to perform I/O-operations with the 612.
If you want to use the extra addresslines as well, you have to take care of
the fact that the original hardware does not know of the addresses above
$0FFFF. So for any decoder reading from/writing to $1C000, $2C000 or any
addres above $0FFFF is equal to reading from/writing to the address
$0C0000. When reading data this will cause busconflicts, when writing data
this cause data to be written to places where it is not wanted. IMHO the
solution for this problem is to disable Clock2 towards the original system.
As far as I know all decoders and/or I/O-ICs in any Commodore use this
signal to decide to become active or not.
I/O-part
The decision to be made is where to place the decoder for the 612 itself:
behind or before the 612. If you place it before the 612 it always will be
accessible but the disadvantage is that it can get it the way when there is
a need to remap certain areas to the area the 612 occupies. If you place it
behind the 612 and you make a mistake with programming the 612, it is
possible you cannot acces the 612 at all anymore meaning you are stuck with
the momentary configuration unless you reset your system.
Practical use.
Andre Fachat built a 2 MHz 65C02 based computer, <A HREF=''>the CS/A65</A>,
using the 74LS610. Some of the above info and ideas are based on his work.
---------------------------------------------------------------------------
Groetjes, Ruud
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