Hi Ruud, I don't have the book here, but I try to clarify what I can remember with the help from my homepage. > > 74LS612 > > The 612 is an IC that enables you to expand your system with 8 extra > addresslines. Notify the fact that I use the word "system" and NOT > processor. The processor won't be aware of those extra addresslines. In > case of the 6502/6510 the processor still only can address 64 KB. > > > How do these 8 extra addresslines fit in the system? > [...] The problem that is confusing is that the C128 chip is called "MMU". I wouldn't do so, but it is now fact. Therefore I would always use C128-MMU or so when this chip is meant. For me the '610 qualifies much more as an MMU. [I have even managed to do some write-protection on 4k block basis with my design: Mapping the the MMU to the I/O space at a second address differing by one address bit (of A4-11) and connecting this address line to DX of the MMU (X a previously unused data line, after r/w handling, i.e. only on writes) gives another "address line" MOX. This is now used to disable the data bus '245 and to set the bus r/w line high when reset (only if no I/O is selected of course). Now writing to $eff0 (MMU register 0) maps a page in CPU $0*** read/write, while writing to $ef70 maps the same page write-protected :-))) Now tell me this is not a 'real' MMU ;-) This schematic is not on the net so far.] > The 74LS612 is a kind of MMU but WITHOUT the multiplexers. These have to be "This means it provides the _address lines_ like the original CPU, only more of them and nothing else. The decoders/multiplexers that translate the address to the chip select lines must be ..." > added by the user. Another difference is that the behaviour of the MMU is > preprogrammed in the factory and cannot be changed. But with the 612 the > user can program its behaviour any time. Speaking in MMU-terms this would > mean that we could program the MMU in such away that BANK 0 behaves like > BANK 3, BANK 3 and 1 as 1 and BANK 2 as 1 as well. What does that mean? I don't get the point here. If I find it again and you like it I can dig out an old tex graphics I produced to show how I used the '610 in my CS/A65. On the left it has the 64k address space divided into 16 blocks a 4k, on the right the real (larger) memory with pointers going from the CPU blocks to arbitrary memory blocks. > The 612 has 16 registers of 12 bits each. The normal procedure is to > address these registers by four addresslines. Four bits of the output are > used to replace the original four addresslines, the other eight bits to > form the extra eight addresslines. > Reconfiguring the original addresslines gives you the possebility to re- > arange the internal configuration if the hardware. By example in a PET you ^^ > could swap the the range $7000/$7FFF and $F000/$FFFF to test a new Kernal- > ROM. You should probably now define the terms "virtual memory" and "real memory", with the CPU (virtual) memory address range going from 0-64k and real from $000000 to $ffffff. > The extra eight lines can be used to add extra memory (RAM, ROM) or I/O in > any way you want. A very nice example is to connect a complete 1541 to your > own system by means of a small interface which replaces the original 6502. Uh, I have to finally draw that schematics in xfig.... (I have a CS/A65 board that does that) > Now you can reconfigure your own system in such a way that it sees the > range $0000/$BFFF of the 1541 as its own and its former own area ^ mapped e.g. in $01**** real memory > $6000/$9FFF as area $C000/$FFFF. In this way you comfortably can test a new ^ from $00**** > Kernal for the 1541. > > > Pinouts. > > +---------------------+ > RS2 -+ 1 40 +- +5V > | | > MA3 -+ 2 39 +- MA2 > | | > RS3 -+ 3 38 +- RS1 > | | > CS -+ 4 37 +- MA1 /CS > | | > STROBE -+ 5 36 +- RS0 /STROBE > | | > R/W -+ 6 35 +- MA0 > | | > D0 -+ 7 34 +- D11 > | | > D1 -+ 8 33 +- D10 > | | > D2 -+ 9 32 +- D9 > | | > D3 -+ 10 31 +- D8 > | 74LS612 | > D4 -+ 11 30 +- D7 > | | > D5 -+ 12 29 +- D6 > | | > MM -+ 13 28 +- NC C on some variants (I think my own pinout description is wrong here about the variants...) > | | > MO0 -+ 14 27 +- MO11 > | | > MO1 -+ 15 26 +- MO10 > | | > MO2 -+ 16 25 +- MO9 > | | > MO3 -+ 17 24 +- MO8 > | | > MO4 -+ 18 23 +- MO7 > | | > MO5 -+ 19 22 +- MO6 > | | > GND -+ 20 21 +- ME /ME > | | > +---------------------+ > > > Pin functions: > > D0 thru D11 Connection to the databus when programming the registers > RS0 thru RS3 Connection to the addressbus when programming the > registers, normally A0 thru A3 > R/W Read, active (H) and Write, active (L) > STROBE input to enter data into choosen register, active (L) > CS ChipSelect, active (L) > MA0 thru MA3 connection to the addressbus during normal operation ^would normally be A12-15 of a 6502 > MO0 thru MO11 The generated addresslines ^would normally be A12-A23 of a 6502+MMU system > MM Map Mode input. When (H), MO0/MO3 reflect MA0/MA3, ^ uhm, I think I once fell for this bug too. AFAIR it's reflected at MO8-11, not MO0-3. Then MO0-7 would be low. > MO4/MO11 are (L). When (L), MO0/MO11 reflect the 12 bits > of the choosen register. > ME When (H), MO0/MO11 are tristate else active. > NC Not connected. C Latch clock input to save the output before changing the address lines. '610 and '611 only. You should probably have a look at the internal diagram, which makes most things clear: http://www.tu-chemnitz.de/~fachat/8bit/hardware/chips/ls610/ls610b.gif > > > 74LS610, 74LS611 and 74LS613. > > The 610 is an 612 plus an extra 12 bits latch. With the 612 MO0/MO11 always > react on the behaviour of MA0/MA3 and MM. With the 610 you can freeze the > output as long as you want. This is archieved with an extra inputline at > pin 28, C (= Clock). A (H) on this input will the 610 behave like a 612, a > (L) freezes the configuration. > The 611 and 613 are the Open Collector versions of the 610 and 613. Oops. :-) > > [...] > Connecting the 612 to a 6502. > > Connecting a 612 to a 6502 can be split up in two parts anyway: the memory- > part and the I/O-part. > > Memory-part. > > If you only want to reconfigure your system within its own 64 KB, then you > only have to "cut" the addresslines A12 thru A15 and to place the 612 in > the created gap. Practically this probably means you replace the processor > by a small circuitboard with onboard the original processor, the 612 and > some logic to perform I/O-operations with the 612. > If you want to use the extra addresslines as well, you have to take care of > the fact that the original hardware does not respond to addresses above > $0FFFF. The original does not know the extra addresslines so to any decoder > the address $0C000 is equal to $1C000, $2C000 and so on. IMHO the solution Probably better: when reading $1c000 or $2c000 etc. the original will still feel addresses at $0c000, as it does not see the additional address lines > for this problem is to disable Clock2 towards the original system. As far > as I know all decoders and/or I/O-ICs in any Commodore use this signal to > decide to become active or not. Outch. I am not really sure about that. This would disable all timers, make some of the chips (I think, the ones that are not static devices and have a minimum clock frequency specified) loose memory. I have used single-direction drivers for the address bus and a '245 for the data bus as connection between the CS/A65 busses (after the MMU) and the original system. The '245 was disabled when the original system was not addressed (i.e. $x**** with x>0; well I actually use $2**** for the emulation so it was x!=2, but you get the point) and also the r/w line was driven high to the original system (read). This is not perfect, however. In fact you would have to make the address lines show a "safe" address to the original system, as otherwise accessing e.g. $1dc0d would read CIA 1 ICR in a C64, and we all know what this means... But on the other hand, stopping the Phi2 is probably exactly what you want to debug other software :-) > > I/O-part > > The decision to be made is where to place the decoder for the 612 itself: > behind or before the 612. If you place it before the 612 it always will be > accessible but the disadvantage is that it can get it the way when there is > a need to remap certain areas to the area the 612 occupies. If you place it > behind the 612 and you make a mistake with programming the 612, it is > possible you cannot acces the 612 at all anymore meaning you are stuck with > the momentary configuration unless you reset your system. in my CS/A65 I have used the "decoder on the CPU side" version, but there is a way to disable it (and also to make the I/O area selected by this decoder appear somewhere mirrored in the real address space (on the BIOS board, description see below). > Practical use. > > Andre Fachat built a 4 MHz 65C02 based computer, <A HREF=''>the CS/A65</A>, http://www.tu-chemnitz.de/~fachat/8bit/hardware/csa/index.html Uh. It's running at 2MHz, but needs a 4MHz CPU to meet the timing. The 4MHz has earlier address line outputs, which makes MMU mapping at 2Mhz possible. There _is_ some delay in the MMU (plus drivers, plus bus delays safety margins, plus memory decoder delays...)! > using the 74LS610. Some of the above info and ideas are based on his work. > > --------------------------------------------------------------------------- > > Questions: > > 1) Why do you use a 610 as you don't have any specific use for the > onboard latch? (Answer: because I just happened to have one ???) NO!!! The latch is used! (I was already looking for a place for this comment. The internal RAM in the '610 is not dual-ported. With the /CS input the address lines for the internal RAM are selected, either MA0-3 or RS0-3. The output of the RAM then reflects the value of the appropriate register. Imagine addressing the MMU with a "decoder behind MMU" setup. The MA0-3 lines are switched off, instead the register chosen with RS0-3 (normally A0-3) gives the output. This is possibly different from the MA0-3-selected register, meaning that the MMU is suddenly deselected again. Therefore I use Phi2 to time-share the MMU: Phi2 low maps the MA0-3 to MO0-7, and the latch (clocked with /Phi2) saves the output value. Then only when Phi2 is high the /CS line is allowed to go low, accessing a different MMU register. But this doesn't hurt anymore because the latch has saved the output value the half cycle before. > > 2) Why do you use IC16 to disconnect the 610 from the bus instead of > using the 610s own capability to do so? I thought the IC16 (a 74LS245) can drive more devices on the bus. But this is indeed a valid question. > 3) You placed the decoder for the 612 before the 612 meaning you always > can access the 612 on the same address, $E800, whatever the > configuration is. On the other hand you say you use your CS/A65 to > test new ROMs for the 1541, meaning you need the whole range from > $C000 thru $FFFF. This is an conflicting situation. > I noticed you have a inputline to disable IOSEL. Activating this line > when you address the area $C000/$FFFF when testing the 1541 ROM means > you are stuck to this configuration until a reset. > How do you handle this particular situation? On the BIOS board there is a configuration register. (IC4 and IC5) With it I can enable the /IOINH line on the CPU board, that disables I/O access on CPU $e800-$efff no matter what the MMU says. But I can also enable the the mapping of the I/O address space in real $0b000 of mapped memory address space via the /EXTIO line. Real $0**** is mapped by the BIOS board and basically IC2 on the BIOS board enables /EXTIO on the bus when Real $0b*** is addressed, making the CPU board lower the /IOSEL line. [This is a (minor) design flaw. /IOSEL should have been open-collector and instead of pulling /EXTIO the BIOS board should pull /IOSEL itself.... But it's the only design flaw I have discovered so far :-) ] So to test the VC1541, I would enable $0b*** I/O mapping, map real $0b*** to, say, CPU $9*** in CPU address space, and disable the CPU $E8** I/O mapping. voila. But then, when testing the new VC1541 ROMs, I always used RESET to return to OS/A65 anyway... :-) > 4) Why do you use 245s instead of the more power friendly 541? Because I didn't know about the 541. Do they also have the same solder-friendly pinout (sometimes I even use '245 for uni-directional drivers because of that)? > At the moment I'm working out an idea of combining a 65816 and a 74LS610. I wonder if this is necessary. Esp. as the '610 is not really fast, and when you want to have the 65816 running at speed.... I was thinking about using a 65816 at 8 MHz, with (Ah, I love those new RAM chips...) _one_ 512k static RAM chip (expensive, but so what... :-) and a divide-by-four cicuitry to use the CS/A65 memory/I/O at 2MHz. It would indeed not be possible to do those nice mapping tricks with this setup, but I don't want to use it for that anyway. It might, however, be useful to map slower I/O stuff around when you are more interested in speeding up/debugging original 8032/VIC20 or even C64 programs. But remember, the delay in the MMU is not neglectable, esp. when running with higher speeds. I really have to dig out my old TeX file with the CS/A65 and OS/A65 1.3 description. hope it helps Andre -- Email address may be invalid. Use "fachat AT physik DOT tu-chemnitz DOT de" ------Fight SPAM - join CAUCE http://www.cauce.org------Thanks, spammers... Andre Fachat, Institute of physics, Technische Universität Chemnitz, FRG http://www.tu-chemnitz.de/~fachat
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